Field effect transistors that are used in power applications or RF applications must switch significant amounts of current at very high frequencies. The downscaling of these field effect transistors helps reduce the total source to drain resistance and the junction capacitances; both can enhance the power handling capability of the device at high frequencies. As the transistor scales to smaller channel lengths, the gate linewidth gets narrower and the sheet resistance contribution to the RC delay increases, drastically impacting the performance in an RF application. While power transistors do not necessarily have to switch at high speeds, this RC delay increase impacts how uniformly the transistor switches. If a power transistor does not uniformly switch, localized regions of the transistor may be required to conduct more current than can reliably be handled, resulting in destruction of the power transistor. Because of these requirements, various solutions for the processing of low resistivity gate material in conjunction with low resistivity contacts to the source and drain of the transistor have been explored.
One approach for obtaining low resistivity gate material is to use refractory metals such as molybdenum. While providing an extremely low resistivity, molybdenum does require special processing and care such that the deposited film does not lead to unwanted traps in the gate oxide, is completely passivated from oxidizing ambients, and there is a means to reliably etch the material for pattern generation. Also, the molybdenum gate does not address the low contact resistance required in the source and drain regions.
Another approach uses tungsten silicide to form the low resistivity gate of the field effect transistor. Tungsten silicide is able to withstand high process temperatures and provides a resultant resistivity of approximately 70E-6 ohm-cm. This silicide is formed through a cosputtering process of the mixture of metal and silicon. The stability of tungsten silicide during high temperature processing and its means of deposition make it suitable for a polycide process, but it also does not address the source and drain contact regions.
As opposed to the polycide processing, many low-power, low-voltage technologies utilize techniques that silicide the polysilicon gates as well as the active source and drain regions of the transistor. This provides both improved gate resistivity and reduced source/drain resistance required for fast switching. A shortcoming of this approach is that it precludes the manufacturing of high-voltage components as the silicide in both the source and drain regions is adjacent to the poly gate spaced by the sidewall oxide. This results in low voltage transistors through the impact of BVdss. Typical materials used in these techniques are titanium and platinum. Titanium-silicide has a resistivity of approximately 13E-06 to 16E-06 ohm-cm, while platinum-silicide has a resistivity of approximately 28E-06 to 35E-06 ohm-cm. Neither of these materials can withstand the high temperature processing as tungsten silicide can, so this temperature limitation forces the processing to be near the end of the manufacturing process where temperature budgets are much less.